Modern high speed processors are demanding higher performance and higher capacities from their main storage subsystems at the same time that price competition is forcing computer manufacturers to tightly control production costs. Dynamic random access memory (DRAM) producers are responding to the performance need by expanding upon the basic fast-page mode (FPM) architecture that has been prevalent in the industry, and whose stability has produced commodity pricing, into a confusing explosion of new architectures, such as Synchronous DRAM (SDRAM), Extended-Data-Out (EDO) and BurstEDO. For a period of time, until stability returns to the DRAM market, there will be uncertainty as to the future price and availability of these competing architectures.
This explosion of varied and new architectures for system memory has caused instability for system memory controller designers who must bet on which architecture is going to win the competition and become the industry standard. Since the architectures are radically different and a system memory controller designed for one architecture typically does not operate with others, the incorrect choice could result in lower profit margins, constrained shipments due to DRAM allocation, or delayed shipments due to redesign for another DRAM type.
In an attempt to ward off the dangers of selecting the wrong architecture, system memory controllers are being designed with multiple, different DRAM interfaces. However, there are three (3) major disadvantages to this solution:
1. The system memory controller design is more complex. All modes must be simulated and tested, which adds to the design time and adds functionality risk. PA1 2. Given a finite system memory controller resource, the extra mode support may limit the optimization of other controller functions that have greater impact to system performance than does the memory interface. PA1 3. Memory performance may vary greatly, depending upon which DRAM architecture is attached due to the variation in bandwidth inherent in the device protocols. Thus, system performance varies accordingly--a competitive problem.
Based on the foregoing, a need exists for a mechanism which enables a system memory controller to be designed with a single common interface, yet usable in accessing multiple types of memory devices. Additionally, a need exists for a mechanism which enables a system memory controller to be designed without regard for the type of memory device to be accessed by the controller. Further, a need exists for a mechanism that enables a system memory controller to be designed in such a manner that the disadvantages described above are eliminated. Yet further, a need exists for a mechanism which enables a system memory controller to be designed with optimum performance, cost and stability.